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| AT28LV010 Features * * * * * * * * * * Single 3.3V 10% Supply Fast Read Access Time - 200 ns Automatic Page Write Operation Internal Address and Data Latches for 128-Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle Time - 10 ms Maximum 1 to 128-Byte Page Write Operation Low Power Dissipation 15 mA Active Current 20 A CMOS Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology Endurance: 100,000K Cycles Data Retention: 10 Years JEDEC Approved Byte-Wide Pinout Commercial and Industrial Temperature Ranges 1 Megabit (128K x 8) Low Voltage Paged CMOS E2PROM Description The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Programmable Read Only Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 A. (continued) Pin Configurations Pin Name A0 - A16 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don't Connect PDIP Top View AT28LV010 PLCC Top View TSOP Top View 0395A 2-155 Description (Continued) The AT28LV010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128-bytes simultaneously. During a write cycle, the address and 1 to 128-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel's 28LV010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. Software data protection is implemented to guard against inadvertent writes. The device also includes an extra 128-bytes of E2PROM for device identification or tracking. Block Diagram Absolute Maximum Ratings* Temperature Under Bias................. -55C to +125C Storage Temperature...................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ................... -0.6V to +6.25V All Output Voltages with Respect to Ground .............-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ................... -0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2-156 AT28LV010 AT28LV010 Device Operation READ: The AT28LV010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their system. WRITE: The write operation of the AT28LV010 allows 1 to 128-bytes of data to be written into the device during a single internal programming period. Each write operation must be preceded by the software data protection (SDP) command sequence. This sequence is a series of three unique write command operations that enable the internal write circuitry. The command sequence and the data to be written must conform to the software protected write cycle timing. Addresses are latched on the falling edge of WE or CE, whichever occurs last and data is latched on the rising edge of WE or CE, whichever occurs first. Each successive byte must be written within 150 s (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28LV010 will cease accepting data and commence the interal programming operation. If more than one data byte is to be written during a single programming operation, they must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same. The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28LV010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28LV010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28LV010 in the following ways: (a) VCC power-on delay - once VCC has reached 2.0V (typical) the device will automatically time out 5 ms (typical) before allowing a write: (b) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (c) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: The AT28LV010 incorporates the industry standard software data protection (SDP) function. Unlike standard 5-volt only E2PROM's, the AT28LV010 has SDP enabled at all times. Therefore, all write operations must be preceded by the SDP command sequence. The data in the 3-byte command sequence is not written to the device; the addresses in the command sequence can be utilized just like any other location in the device. Any attempt to write to the device without the 3-byte sequence will start the internal timers. No data will be written to the device. However, for the duration of tWC, read operations will effectively be polling operations. 2-157 DC and AC Operating Range AT28LV010-20 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 3.3V 5% AT28LV010-25 0C - 70C -40C - 85C 3.3V 10% Operating Modes Mode Read Write (2) Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable CE VIL VIL VIH X X X OE VIL VIH X (1) WE VIH VIL X VIH X X I/O DOUT DIN High Z X VIL VIH High Z Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. DC Characteristics Symbol ILI ILO ISB ICC VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA; VCC = 3.0V IOH = -100 A; VCC = 3.0V 2.4 2.0 .45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC + 1V f = 5 MHz; IOUT = 0 mA; VCC = 3.6V Com. Ind. Min Max 1 1 20 50 15 0.8 Units A A A A mA V V V V 2-158 AT28LV010 AT28LV010 AC Read Characteristics AT28LV010-20 Symbol tACC tCE tOE tDF tOH (1) (2) (3, 4) AT28LV010-25 Min Max Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first Min Max Units ns ns ns ns ns 200 200 0 0 0 80 55 0 0 0 250 250 100 60 AC Read Waveforms (1, 2, 3, 4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level Output Test Load tR, tF < 5 ns Pin Capacitance (f = 1 MHz, T = 25C) (1) Typ CIN COUT Note: Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 4 8 1. This parameter is characterized and is not 100% tested. 2-159 AC Write Characteristics (1) Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH Note: Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Min 0 100 0 0 200 100 10 Max Units ns ns ns ns ns ns ns 1. All write operations must be preceded by the SDP command sequence. AC Write Waveforms WE Controlled CE Controlled 2-160 AT28LV010 AT28LV010 Software Protected Write Characteristics Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 100 0 100 100 10 200 150 Min Max 10 Units ms ns ns ns ns ns s ns Programming Algorithm LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS (3) LOAD LAST BYTE TO LAST ADDRESS (3) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Data protect state will be re-activated at the end of program cycle. 3. 1 to 128-bytes of data are loaded. WRITES ENABLED (2) ENTER DATA PROTECT STATE Software Protected Program Cycle Waveforms (1, 2, 3) Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3-bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16) must be the same for each high to low transition of WE (or CE). 3. OE must be high only when WE and CE are both low. 2-161 Data Polling Characteristics (1) Symbol tDH tOEH tOE tWR Parameter Data Hold Time OE Hold Time OE to Output Delay (2) Min 10 10 0 Typ Max Units ns ns ns ns Write Recovery Time Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. Data Polling Waveforms Toggle Bit Characteristics (1) Symbol tDH tOEH tOE tOEHP tWR Parameter Data Hold Time OE Hold Time OE to Output Delay (2) OE High Pulse Write Recovery Time 150 0 2. See AC Read Characteristics. Min 10 10 Typ Max Units ns ns ns ns ns Notes: 1. These parameters are characterized and not 100% tested. Toggle Bit Waveforms Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 2-162 AT28LV010 AT28LV010 Ordering Information (1) tACC (ns) 200 ICC (mA) Active 15 Standby 0.2 AT28LV010-20JC AT28LV010-20PC AT28LV010-20TC AT28LV010-20JI AT28LV010-20PI AT28LV010-20TI AT28LV010-25JC AT28LV010-25PC AT28LV010-25TC AT28LV010-25JI AT28LV010-25PI AT28LV010-25TI Ordering Code Package 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) 15 0.2 250 15 0.2 15 0.2 Note: 1. See Valid Part Number table below. Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers AT28LV010 AT28LV010 Speed 20 25 Package and Temperature Combinations JC, JI, PC, PI, TC, TI JC, JI, PC, PI, TC, TI Package Type 32J 32P6 32T 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32 Lead, Plastic Thin Small Outline Package (TSOP) 2-163 |
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